The present invention relates to a system wherein one or more host processors, each having one or more input-output channels, communicate through one or more storage control units to utilize data recorded on a plurality of disk drives. More particularly, the present invention provides a cache/disk subsystem including one or more storage control units and one or more cache storage units. The cache store is transparent to the user who programs the processor as though he was directly addressing the disk drives.
In data processing systems having extremely large electronic memories, it is well known to provide a smaller cache memory having a much faster access time than the main memory. When the processor issues a main memory address, this address is utilized to access an address descriptor table which is normally set associative and contains words identifying which main memory addresses are present in the cache memory. Each entry in the table also includes information identifying certain characteristics of the data at the associated addresses. If the addressed data is present in the cache memory then a transfer is set up between the processor and the cache memory. If the data being addressed is not present in the cache memory then it is retrieved from the main memory, entered into the cache memory, and then accessed for transfer to the processor.
Systems of the type described above have found wide usage where the cache memory and the main memory are both wholly electronic but relatively little use has been made of the cache memory concept in conjunction with disk devices. The present invention provides a cache memory for use with a plurality of disk devices, the arrangement being such that commands from a host processor may be queued for latter execution if an addressed disk device is busy or has other commands queued and waiting to be executed. Plural storage control units may be provided, each having access to the queues so that a queued command may be executed by either storage control unit.